Thursday, November 03, 2005

Chip Design in Taiwan and China Improving

Chip designers in Taiwan and China are become ever more technologically skilled, reports this site.

Seventy-three percent of designers in China and Taiwan are designing ASICs at 180 nanometer or below, an increase of 21 percentage points from 2004, according to the results of an annual study by Global Sources Ltd. and Gartner Inc.

For standard IC projects, 52 percent of desingers in China and Taiwan are using 180 nanometer or finer line widths, 10 percentage points higher than 2004, according to the joint study, titled "Design Trends &
Electronic Design Automation (EDA) Tools: Mainland China & Taiwan."

Global Sources and Gartner surveyed 378 engineers in China and 226 in Taiwan
for a study that compares design trends and use of EDA tools in both regions.

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